View MT48H8M16LF_1285121.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

128Mb: x16 - Mobile SDRAM Features
Synchronous DRAM
MT48H8M16LF - 2 Meg x 16 x 4 banks
Features
* Temperature compensated self refresh (TCSR) * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge * Programmable burst lengths: 1, 2, 4, 8, or full page * Auto precharge, includes concurrent auto precharge, and auto refresh modes * Self refresh mode; standard and low power * 64ms, 4,096-cycle refresh * LVTTL-compatible inputs and outputs * Low voltage power supply * Partial array self refresh power-saving mode * Deep power-down mode * Programmable output drive strength * Operating temperature ranges: Extended (-25C to +85C) Industrial (-40C to +85C)
Figure 1: 54-Ball FBGA Assignment (Top View)
1 A B C D E F G H J
VSS
2
DQ15
3
VSSQ
4
5
6
7
VDDQ
8
DQ0
9
VDD
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
NC
VSS
VDD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
NC/A12
A11
A9
BA0
BA1
CS#
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
Options
* VDD/VDDQ 1.8V/1.8V * Configurations 8 Meg x 16 (2 Meg x 16 x 4 banks) * Package/Ball out 54-ball FBGA, 8mm x 8mm (standard) 54-ball FBGA, 8mm x 8mm (lead-free) * Timing (Cycle Time) 8ns @ CL = 3 (125 MHz) 9.6ns @ CL = 3 (104 MHz) * Operating Temperature Extended (-25C to +85C) Industrial (-40C to +85C)
Marking
H 8M16 F4 B4 -8 -10 none IT
Configuration Refresh Count Row Addressing Bank Addressing Column Addressing
Top View (Ball Down)
Table 1:
Address Table
8 Meg x 16 2 Meg x 16 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 512 (A0-A8)
Table 2:
Key Timing Parameters
CL = CAS (READ) latency Access Time CL = 2 - 8ns 8ns CL = 3 6ns 7ns - -
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron Web site, www.micron.com/decoder.
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_1.fm - Rev. E 3/05 EN
Speed Grade -8 -10 -8 -10
Clock Frequency 125 MHz 104 MHz 104 MHz 83 MHz
Setup Hold Time Time 2.5ns 2.5ns 2.5ns 2.5ns 1ns 1ns 1ns 1ns
1
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128Mb: x16 Mobile SDRAM Table of Contents Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 FBGA Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Temperature Compensated Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Partial Array Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 COMMAND INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 BURST READ/SINGLE WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16TOC.fm - Rev. E 3/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM List of Figures List of Figures
Figure 1: Figure 2: Figure 3: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: 54-Ball FBGA Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Part Numbering Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 8 Meg x 16 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Extended Mode Register Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Activating a Specific Row in a Specific Bank Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 READ-To-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 READ-To-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 READ-To-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 WRITE-To-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 WRITE-To-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 WRITE-To-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 READ - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Single READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Single READ - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 READ - Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 READ - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 WRITE - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 WRITE - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Single WRITE - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Single WRITE - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Write - Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Write - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 54-Ball FBGA (8mm x 8mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
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128Mb: x16 Mobile SDRAM List of Tables List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Truth Table 1 - Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Truth Table 2 - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Truth Table 3 - Current State BanK n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Truth Table 4 - Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 AC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .40 AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 IDD7 - Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM General Description Figure 2: Part Numbering Diagram
Example Part Number: MT48H8M16LFF4-8 IT - MT48 VDD/ VDDQ Configuration Package Speed Temp
Operating Temp VDD/VDDQ 1.8/1.8V H None IT Extended Industrial
Configuration 8 Meg x16 8M16LF
Package 54-ball VFBGA (8mm x 8mm) 54-ball VFBGA (8mm x 8mm) Lead-Free F4 B4 -8 -10
Speed Grade 8ns 9.6ns
General Description
The Micron(R) 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 32,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, deep power-down mode. All inputs and outputs are LVTTL-compatible.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM General Description
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
Figure 3: 8 Meg x 16 SDRAM Functional Block Diagram
CKE CLK CS# WE# CAS# RAS# CONTROL LOGIC
BA1 0 0 1 1
BA0 0 1 0 1
Bank 0 1 2 3
COMMAND DECODE
BANK3 BANK2 BANK1
MODE REGISTER
REFRESH 12 COUNTER
12 12
ROWADDRESS MUX
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK0 MEMORY ARRAY (4,096 x 512 x 16)
2
2 DQML, DQMH
SENSE AMPLIFIERS 16 4096
DATA OUTPUT REGISTER
2 A0-A11, BA0, BA1 ADDRESS REGISTER BANK CONTROL LOGIC
14
I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 16 512 (x16)
16
DQ0DQ15
2
DATA INPUT REGISTER
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH 9
8
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128Mb: x16 Mobile SDRAM General Description Table 3:
F2
Ball Descriptions
SYMBOL CLK TYPE Input DESCRIPTION Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank), DEEP POWER-DOWN (all banks idle), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the command being entered. Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0-DQ7, UDQM corresponds to DQ8-DQ15. LDQM and UDQM are considered same state when referenced as DQM. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These balls also select between the mode register and the extended mode register. Address Inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output: Data bus.
54-BALL FBGA
F3
CKE
Input
G9
CS#
Input
F7, F8, F9 E8, F1
CAS#, RAS#, WE# LDQM, UDQM
Input Input
G7, G8
BA0, BA1
Input
H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2
A0-A11
Input
A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 E2, G1
DQ0-DQ15
I/O
NC
-
A7, B3, C7, D3 A3, B7, C3, D7 A9, E7, J9 A1, E3, J1
VDDQ VSSQ VDD VSS
Supply Supply Supply Supply
Internally Not Connected: These could be left unconnected, but it is recommended they be connected or VSS. G1 is a no connect for this part but may be used as A12 in future designs. DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Core Power Supply. Ground.
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128Mb: x16 Mobile SDRAM Functional Description
Functional Description
In general, the 128Mb SDRAMs (2 Meg x 16 x 4 banks) are quad-bank DRAMs that operate at 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16's 32,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (A0-A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power should be applied to VDD and VDDQ simultaneously. Once the power is applied to VDD and VDDQ, and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or NOP commands should be applied. Once the 100s delay has been satisfied with at least one command inhibit or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO refresh cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command.
Mode Register Definition
In order to achieve low power consumption, there are two mode registers in the mobile component, mode register and extended mode register. The mode register is illustrated in Figure 4, "Mode Register Definition," on page 11 (the extended mode register is illustrated in Figure 6, "Extended Mode Register Diagram," on page 14). The mode register defines the specific mode of operation of the SDRAM, including burst length, burst type, CAS latency, operating mode, and write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10, and M11 should be set to zero. M12 and M13 should be set to zero to prevent extended mode register. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
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128Mb: x16 Mobile SDRAM Mode Register Definition Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4, "Mode Register Definition," on page 11. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A0-A8 when the burst length is set to two; by A2-A8 when the burst length is set to four; and by A3-A8 when the burst length is set to eight.
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128Mb: x16 Mobile SDRAM Mode Register Definition Table 4: Burst Definition
Order of Accesses Within a Burst Burst Length 2 Starting Column Address Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2, Cn+3, Cn+4..., ...Cn-1, Cn... Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported
A0
0 1
A1
4 0 0 1 1
A0
0 1 0 1
A2
0 0 0 0 1 1 1 1
A1
0 0 1 1 0 0 1 1 n = A0-A8 (location 0-y)
A0
0 1 0 1 0 1 0 1
8
Full Page (y)
Notes: 1. For full-page accesses: y = 512. 2. For BL = 2, A1-A8 select the block-of-two burst; A0 selects the starting column within the block. 3. For BL = 4, A2-A8 select the block-of-four burst; A0-A1 select the starting column within the block. 4. For BL = 8, A3-A8 select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A8 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For BL = 1, A0-A8 select the unique column to be accessed, and mode register bit M3 is ignored.
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128Mb: x16 Mobile SDRAM Mode Register Definition Figure 4: Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
M13 M12 M11 M10 M9 M8 13 12 11 10 9 8
M7 M6 7 6
M5 5
M4 4
M3 3 BT
M2 2
M1 1
M0 0 Mode Register (Mx)
Reserved** Reserved* WB
Op Mode
CAS Latency
Burst Length
*Should program M10 = "0, 0" to ensure compatibility with future devices.
Burst Length M2 M1 M0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
** BA1, BA0 = "0, 0" to prevent Extended Mode Register.
1 1 1 1
M3 0 1
Burst Type Sequential Interleaved
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
M8 0 -
M7 0 -
M6-M0 Defined -
Operating Mode Standard Operation All other states reserved
M9 0 1
Write Burst Mode Programmed Burst Length Single Location Access
Note:
The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 4, "Burst Definition," on page 10.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
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128Mb: x16 Mobile SDRAM Mode Register Definition
the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 5. Table 5 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Figure 5: CAS Latency
T0 CLK COMMAND T1 T2 T3
READ
NOP tLZ
NOP tOH DOUT
DQ tAC CL = 2
T0 CLK COMMAND
T1
T2
T3
T4
READ
NOP
NOP tLZ
NOP tOH DOUT
DQ tAC CL = 3
DON'T CARE UNDEFINED
Table 5:
CAS Latency
Allowable Operating Frequency (MHz) Speed -8 -10 CAS Latency = 2 104 83.3 CAS Latency = 3 125 104
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
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128Mb: x16 Mobile SDRAM Mode Register Definition Extended Mode Register
The extended mode register controls the functions beyond those controlled by the mode register. These additional functions are special features of the mobile device. They include temperature compensated self refresh (TCSR) control, partial array self refresh (PASR), and output drive strength. Not programming the extended mode register upon initialization, will result in default settings for the low power features. The extended mode will default to the +85C setting for TCSR, full drive strength, and full array refresh. The extended mode register is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and retains the stored information until it is programmed again or the device loses power. The extended mode register must be programmed with E6 through E11 set to "0." It must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Once the values are entered the extended mode register settings will be retained even after exiting deep power-down.
Temperature Compensated Self Refresh
Temperature compensated self refresh (TCSR) allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller have to select the maximum TCSR level. This would guarantee data during SELF REFRESH. Every cell in the SDRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures, a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. Historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. Adjusting the refresh rate by setting E4 and E3 allows the SDRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the SDRAM is operating at normal temperatures.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the partial array self refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank (bank 0). Also included in the refresh options are the 1/2 bank and 1/4 bank partial array self refresh (bank 0). WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during SELF REFRESH. It is important to note that data in unused banks, or portions of banks, will be lost when PASR is used. Data will be lost in banks 1, 2, and 3 when the one bank option is used.
Driver Strength
Bits E5 and E6 of the extended mode register can be used to select the driver strength of the DQ outputs. This value should be set according to the application's requirements. Full drive strength was carried over from standard SDRAM and is suitable to drive higher load systems. Full drive strength is not recommended for loads under 30pF. Half drive
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128Mb: x16 Mobile SDRAM Mode Register Definition
strength is intended for multi-drop systems with various loads. This drive option is not recommended for loads under 15pF. Quarter drive strength is intended for lighter loads or point-to-point systems.
Figure 6: Extended Mode Register Diagram
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 13 12 11 10 1 9 8 7 6
DS
5
4 TCSR
3
2
1
0
0 All must be set to "0"
PASR
Extended Mode Register (Ex)
E6 E5 Driver Strength 0 0 Full Strength3 0 1 Half Strength 1 0 Quarter Strength 1 1 Reserved
E4 1 0 0 1
E3 Maximum Case Temp 1 0 1 0 85C3 70C 45C
15C
E2 0 0 0 0 1 1 1 1
E1 0 0 1 1 0 0 1 1
E0 0 1 0 1 0 1 0 1
Self Refresh Coverage
Four Banks3 Two Banks (Bank 0,1) One Bank (Bank 0) RFU RFU 1/2 Bank (Bank 0)4 1/4 Bank (Bank 0)5 RFU
Notes: 1. E13 and E12 (BA1 and BA0) must be "1, 0" to select the extended mode register (vs. the base mode register). 2. RFU: Reserved for future use. 3. Default EMR values are full array for PASR, full drive strength, and 85 for TCSR. 4. E11 = 0. 5. E10, E11 = 0.
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128Mb: x16 Mobile SDRAM Commands
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following "Operation" on page 18; these tables provide current state/next state information.
Table 6:
Truth Table 1 - Commands and DQM Operation
Note 1 CS# RAS# CAS# WE# H L L L L L L L L X X X H L H H H L L L X X X H H L L H H L L X X X H H H L L L H L X X DQM X X X L/H L/H X X X X L H ADDR X X Bank/Row Bank/Col Bank/Col X Bank, A10 X Op-Code X X DQs X X X X Valid X X X X Active High-Z Notes
Name (Function) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE or DEEP POWER-DOWN (Enter deep power-down mode) PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER/LOAD EXTENDED MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z Notes: 1. 2. 3. 4.
3 4 4 9, 10 5 6, 7 2 8 8
5. 6. 7. 8. 9. 10.
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN. A0-A11 define op-code written to mode register. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. A0-A8 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQML controls DQ0-7, DQMH controls DQ8-15. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when CKE is LOW. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on the bus. However the DQs column reads a "Don't Care" state to illustrate that the BURST TERMINATE command can occur when there is no data present.
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128Mb: x16 Mobile SDRAM Commands COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0-A11, BA0, BA1. See "Mode Register Definition" on page 8. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. The values of the mode register and extended mode register will be retained even when exiting deep power-down.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQ subject to the logic level on the DQM inputs 2 clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only 1 bank is to be
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128Mb: x16 Mobile SDRAM BURST TERMINATE
precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in "Operation" on page 18.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in "Operation" on page 18.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in "Operation" on page 18. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO REFRESH command every 15.625s will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down, as long as power is not completely removed from the SDRAM. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that.
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128Mb: x16 Mobile SDRAM Deep Power-Down
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands should be issued at once and then every 15.625s or less, as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.
Deep Power-Down
The operating mode deep power-down achieves maximum power reduction by eliminating the power of the whole memory array of the device. Array data will not be retained once the device enters deep power-down mode. This mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# held HIGH at the rising edge of the clock, while CKE is LOW. This mode is exited by asserting CKE HIGH.
Operation
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 7 on page 19). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 8 on page 19, which covers any case where 2 < tRCD (MIN)/tCK 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD.
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128Mb: x16 Mobile SDRAM READs Figure 7: Activating a Specific Row in a Specific Bank Register
CLK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A10, A11
ROW ADDRESS
BA0, BA1
BANK ADDRESS
DON'T CARE
Figure 8: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3
T0 CLK T1 T2 T3 T4
COMMAND
ACTIVE
NOP
NOP
READ or WRITE
tRCD
DON'T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 9 on page 20. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent dataout element will be valid by the next positive clock edge. Figure 5, "CAS Latency," on page 12, shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the
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128Mb: x16 Mobile SDRAM READs
last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 10, "Consecutive READ Bursts," on page 21 for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 11, "Random READ Accesses," on page 22, or each subsequent READ may be performed to a different bank. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command.
Figure 9: READ Command
CLK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A8
COLUMN ADDRESS
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE BANK ADDRESS
BA0,1
DON'T CARE
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128Mb: x16 Mobile SDRAM READs Figure 10: Consecutive READ Bursts
T0 CLK T1 T2 T3 T4 T5 T6
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
X = 1 cycle
ADDRESS
BANK, COL n
BANK, COL b
DQ
CL = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK, COL n
BANK, COL b
DQ
CL = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
TRANSITIONING DATA
DON'T CARE
Note:
Each READ command may be to any bank. DQM is LOW.
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128Mb: x16 Mobile SDRAM READs Figure 11: Random READ Accesses
T0 CLK T1 T2 T3 T4 T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
CL = 2
DOUT n
DOUT a
DOUT x
DOUT m
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
CL = 3
DOUT n
DOUT a
DOUT x
DOUT m
TRANSITIONING DATA
DON'T CARE
Note:
Each READ command may be to any bank. DQM is LOW.
The DQM input is used to avoid I/O contention, as shown in Figure 12 and Figure 13 on page 23. The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE command (DQM latency is 2 clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQ will go High-Z (or remain HighZ), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 14 on page 24, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 on page 23 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 13 on page 23 shows the case where the additional NOP is needed. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 14 on page 24 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the
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128Mb: x16 Mobile SDRAM READs
PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Figure 12: READ-To-WRITE
T0 T1 T2 T3 T4
CLK DQM
COMMAND ADDRESS
READ
NOP
NOP
NOP
WRITE
BANK, COL n
BANK, COL b
tCK tHZ
DQ
DOUT n
DIN b
tDS
CL = 3
DON'T CARE
Note:
The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required.
Figure 13: READ-To-WRITE with Extra Clock Cycle
T0 CLK DQM T1 T2 T3 T4 T5
COMMAND ADDRESS
READ
NOP
NOP
NOP
NOP
WRITE
BANK, COL n
BANK, COL b
tHZ DQ
DOUT n DIN b
tDS
CL = 3
TRANSITIONING DATA
DON'T CARE
Note:
The READ command may be to any bank, and the WRITE command may be to any bank.
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128Mb: x16 Mobile SDRAM READs Figure 14: READ-To-PRECHARGE
T0 CLK
t RP
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE X = 1 cycle
NOP
NOP
ACTIVE
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ
CL = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
T0 CLK
T1
T2
T3
T4
T5
T6
T7
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ
CL = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
TRANSITIONING DATA
DON'T CARE
Note:
DQM is LOW.
Figure 15: Terminating a READ Burst
T0 CLK T1 T2 T3 T4 T5 T6
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE X = 1 cycle
NOP
NOP
ADDRESS
BANK, COL n
DQ
CL = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK, COL n
DQ
CL = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
TRANSITIONING DATA
DON'T CARE
Note:
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DQM is LOW.
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128Mb: x16 Mobile SDRAM READs
Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 15 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst.
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored (see Figure 18 on page 26). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.)
Figure 16: WRITE Command
CLK CKE HIGH CS#
RAS#
CAS#
WE#
A0-A8 A9, A11
COLUMN ADDRESS
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0,1
BANK ADDRESS
VALID ADDRESS
DON'T CARE
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 19 on page 27. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous
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128Mb: x16 Mobile SDRAM READs
WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a different bank.
Figure 17: WRITE Burst
T0 CLK T1 T2 T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK, COL n
DQ
DIN n
DIN n+1
TRANSITIONING DATA
DON'T CARE
Note:
BL = 2. DQM is LOW.
Figure 18: WRITE-To-WRITE
T0 T1 T2
CLK
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1
DIN b
DON'T CARE
Note:
DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 20 on page 27. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 21 on page 28. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
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128Mb: x16 Mobile SDRAM READs
In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 23 on page 29, where data n is the last desired data element of a longer burst.
Figure 19: Random WRITE Cycles
T0 CLK T1 T2 T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
DIN n
DIN a
DIN x
DIN m
DON'T CARE
Note:
Each WRITE command may be to any bank. DQM is LOW.
Figure 20: WRITE-To-READ
CLK
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1
DOUT b
DOUT b+1
DON'T CARE
CL = 2
Note:
The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW.
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128Mb: x16 Mobile SDRAM Power-Down Figure 21: WRITE-To-PRECHARGE
T0 CLK
tWR @ tCK 15ns
T1
T2
T3
T4
T5
T6
DQM
t RP
COMMAND
WRITE
NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
ADDRESS
BANK a, COL n
t WR
BANK (a or all)
BANK a, ROW
DQ
DIN n
DIN n+1
tWR @ tCK < 15ns
DQM
t RP
COMMAND ADDRESS
WRITE
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
BANK a, COL n
t WR
BANK (a or all)
BANK a, ROW
DQ
DIN n
DIN n+1
DON'T CARE
Note:
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
PRECHARGE
The PRECHARGE command (see Figure 24 on page 30) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See Figure 22 on page 29.
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128Mb: x16 Mobile SDRAM Power-Down Figure 22: Power-Down
CLK tCKS CKE
(( )) (( ))
> tCKS
(( ))
COMMAND
NOP
(( )) (( ))
NOP
ACTIVE
All banks idle Input buffers gated off Enter power-down mode. Exit power-down mode.
tRCD tRAS tRC DON'T CARE
Figure 23: Terminating a WRITE Burst
T0 CLK T1 T2
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK, COL n
(ADDRESS)
DQ
DIN n
(DATA)
TRANSITIONING DATA
DON'T CARE
Note:
DQMs are LOW.
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128Mb: x16 Mobile SDRAM Power-Down Figure 24: PRECHARGE Command
CLK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A9, A11
All Banks
A10
Bank Selected
BA0,1
BANK ADDRESS
VALID ADDRESS
DON'T CARE
Deep Power-Down
Deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. Data on the memory array will not be retained once deep power-down mode is executed. Deep power-down mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep power-down. In order to exit deep power-down mode, CKE must be asserted HIGH. After exiting, the following sequence is needed in order to enter a new command. Maintain NOP input conditions for a minimum of 100s. Issue PRECHARGE commands for all banks. Issue eight or more AUTO REFRESH commands. The values of the mode register and extended mode register will be retained upon exiting deep power-down.
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input balls at the time of a suspended internal clock edge is ignored; any data present on the DQ balls remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figure 25, and Figure 26 on page 31.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.
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128Mb: x16 Mobile SDRAM Power-Down BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).
Figure 25: Clock Suspend During WRITE Burst
T0 CLK T1 T2 T3 T4 T5
CKE
INTERNAL CLOCK
COMMAND
NOP
WRITE
NOP
NOP
ADDRESS
BANK, COL n
DIN
DIN n
DIN n+1
DIN n+2
DON'T CARE
Note:
BL = 4 or greater, and DM is LOW.
Figure 26: Clock Suspend During READ Burst
T0 CLK T1 T2 T3 T4 T5 T6
CKE
INTERNAL CLOCK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
ADDRESS
BANK, COL n
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
Note:
CL = 2, BL = 4 or greater, and DQM is LOW.
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128Mb: x16 Mobile SDRAM Power-Down Concurrent Auto Precharge
Micron SDRAM devices support concurrent auto precharge, which allows an access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing. Four cases where concurrent auto precharge occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, 2 or 3 clocks later, depending on CAS latency. The precharge to bank n will begin when the READ to bank m is registered (Figure 27). 2. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m registers, a READ on bank n will be interrupted. DQM should be used 2 clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (Figure 28).
Figure 27: READ With Auto Precharge Interrupted by a READ
T0 CLK
READ - AP BANK n READ - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
READ with Burst of 4
Interrupt Burst, Precharge t RP - BANK n
Idle tRP - BANK m Precharge
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS DQ
BANK n, COL a
BANK m, COL d DOUT a DOUT a+1 DOUT d DOUT d+1
CAS Latency = 3 (BANK n) CL = 3 (BANK m)
DON'T CARE
Note:
DQM is LOW.
Figure 28: READ With Auto Precharge Interrupted by a WRITE
T0 CLK
READ - AP BANK n Page Active WRITE - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
READ with Burst of 4
Interrupt Burst, Precharge tRP - BANK n
Idle t WR - BANK m Write-Back
Internal States
BANK m
BANK n, COL a
Page Active
WRITE with Burst of 4
ADDRESS 1 DQM DQ
BANK m, COL d
DOUT a CL = 3 (BANK n)
DIN d
DIN d+1
DIN d+2
DIN d+3
DON'T CARE
Note:
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DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
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128Mb: x16 Mobile SDRAM Power-Down
WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): When a READ to bank m registers, it will interrupt a WRITE on bank n, with the data-out appearing 2 or 3 clocks later, (depending on CAS latency). The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 29). 4. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m registers, it will interrupt a WRITE on bank n. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 30).
Figure 29: WRITE With Auto Precharge Interrupted by a READ
T0 CLK
WRITE - AP BANK n READ - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS DQ
BANK n, COL a
DIN a DIN a+1
BANK m, COL d
DOUT d DOUT d+1
CL = 3 (BANK m)
DON'T CARE
Note:
DQM is LOW.
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE
T0
CLK
WRITE - AP BANK n WRITE - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n t WR - BANK m Write-Back
Internal States
BANK m
Page Active BANK n, COL a DIN a DIN a+1 DIN a+2
WRITE with Burst of 4
ADDRESS DQ
BANK m, COL d DIN d DIN d+1 DIN d+2 DIN d+3
DON'T CARE
Note:
DQM is LOW.
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128Mb: x16 Mobile SDRAM Power-Down Table 7:
CKEn-1
Truth Table 2 - CKE
Notes: 1-4; Notes appear below table. CKEn Current State Power-Down Self Refresh Clock Suspend Deep Power-Down Power-Down Deep Power-Down Self Refresh Clock Suspend All Banks Idle All Banks Idle All Banks Idle Reading or Writing Commandn X X X X COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP BURST TERMINATE AUTO REFRESH VALID See Truth Table 3 Actionn Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Maintain Deep Power-Down Exit Power-Down Exit Deep Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Deep Power-Down Entry Self Refresh Entry Clock Suspend Entry Notes
L
L
L
H
8 5 8 6 7 8
H
L
H
H
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 8. Deep power-down is a power-saving feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when CKE is LOW.
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128Mb: x16 Mobile SDRAM Power-Down Table 8: Truth Table 3 - Current State BanK n, Command to Bank n
Notes: 1-6; notes appear below table. Current State Any Idle CS# H L L L L L L L L L L L L L L L L RAS# X H L L L L H H L H H L H H H L H CAS# X H H L L H L L H L L H H L L H H WE# X H H H L L H L L H L L L H L L L Command (Action) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) BURST TERMINATE READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) BURST TERMINATE Notes
Row Active
Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
7 7 11 10 10 8 10 10 8 9 10 10 8 9
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state.
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128Mb: x16 Mobile SDRAM Power-Down
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when t RP is met. Once tRP is met, all banks will be in the idle state. All states and sequences not shown are illegal or reserved. Not bank-specific; requires that all banks are idle. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. Deep Power-Down is power-saving feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when CKE is LOW. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. Does not affect the state of the bank and acts as a NOP to that bank.
6. 7. 8. 9. 10. 11.
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128Mb: x16 Mobile SDRAM Power-Down Table 9: Truth Table 4 - Current State Bank n, Command to Bank m
Notes: 1-6; notes appear below and on next page. Current State Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) CS# H L X L L L L L L L L L L L L L L L L L L L L RAS# X H X L H H L L H H L L H H L L H H L L H H L CAS# X H X H L L H H L L H H L L H H L L H H L L H WE# X H X H H L L H H L L H H L L H H L L H H L L Command (Action) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Any command allowed to bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE Notes
7 7
7, 10 7, 11 9 7, 12 7, 13 9 7, 8, 14 7, 8, 15 9 7, 8, 16 7, 8, 17 9
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved.
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128Mb: x16 Mobile SDRAM Power-Down
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 10 on page 21). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 12 and Figure 13 on page 23). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 20 on page 27), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 18 on page 26). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 27 on page 32). The PRECHARGE to bank n will begin when the READ to bank m is registered. 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 28 on page 32). DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered. 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the dataout appearing CAS latency later (Figure 29 on page 33). The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m. 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered (Figure 30 on page 33). The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m.
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128Mb: x16 Mobile SDRAM Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Voltage on VDD/VDDQ Supply Relative to VSS Voltage on Inputs, NC or I/O Pins Relative to VSS Operating Temperature Extended Industrial Storage Temperature (plastic) Symbol VDD/VDDQ VIN TA -25 -40 -55 +85 +85 +150 MIN -0.35 -0.35 MAX +2.8 +2.8 Units V V C
TSTG
C
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear on page 43; VDD = VDDQ = +1.8V 0.1V Parameter/Condition Supply Voltage I/O Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output High Voltage: All inputs Output Low Voltage: All inputs Input Leakage Current: Any input 0V VIN VDD (All other pins not under test = 0V) Output Leakage Current: DQ disabled; 0V VOUT VDDQ Symbol VDD VDDQ VIH VIL VOH VOL II IOZ MIN MAX Units V V V V V V A A Notes
1.7 1.9 1.7 1.9 0.8 x VDDQ VDD +0.3 -0.3 +0.3 0.9xVDDQ - - 0.2 -1.0 1.0 -1.5 1.5
22 22
Table 11: AC Electrical Characteristics and Operating Conditions
VDD = 1.7V-1.9V; VDDQ = 1.7V-1.9V Parameter/Condition Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Symbol VIH VIL MIN 1.4 MAX +0.4 Units V V Notes
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128Mb: x16 Mobile SDRAM Absolute Maximum Ratings Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11; notes appear on page 43 AC Characteristics Parameter Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time CL = 3 CL = 2 Symbol AC (3) AC (2) t AH t AS t CH t CL tCK (3) tCK (2) tCKH tCKS tCMH tCMS tDH tDS tHZ (3) tHZ (2) tLZ tOH tOH N tRAS tRC tRCD tREF tRFC tRP tRRD tT t WR (a)
t t t
-8 MIN MAX 6 8 1 2.5 3 3 8 9.6 1 1.5 0.5 1.5 1 2.5 1 2.5 3 3 9.6 12 1 2.5 0.5 2.5 1 2.5 MIN
-10 MAX 7 8 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns - ns ns Notes 27
CL = 3 CL = 2
100 100
100 100
23 23
CL = 3 CL = 2
7 8 1 2.5 1.8 48 80 19 80 19 16 0.5 1 CLK +7ns 15 80 1 2.5 1.8 50 100 20 100 20 20 0.5 1 CLK +5ns 15 100
7 8
10 10
28
120,000
120,000
64
64
1.2
1.2
7 24 25 20
Exit SELF REFRESH to ACTIVE command
WR (m) t XSR
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128Mb: x16 Mobile SDRAM Absolute Maximum Ratings Table 13: AC Functional Characteristics
Notes: 5, 6, 7, 8, 9, 11; notes appear on page 43 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command Symbol
t
-8 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2
-10 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2
Units
t
Notes 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17
CCD
CK
tCKED
tCK t t
PED DQD tDQM t DQZ tDWD t DAL tDPL tBDL t CDL tRDL tMRD
t
t
CK CK tCK t CK tCK t CK tCK tCK t CK tCK tCK
tCK tCK
CL = 3 CL = 2
tROH(3) tROH(2)
Table 14: IDD Specifications and Conditions
Notes: 1, 5, 6, 11, 13, 32; notes appear on page 43; VDD = VDDQ = +1.8V 0.1V MAX Parameter/Condition Operating Current: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) Standby Current: Power-Down Mode; All banks idle; CKE = LOW Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress Operating Current: Burst Mode; Continuous burst; READ or WRITE; All banks active tRC = tRFC (MIN) Auto Refresh Current tRFC = 15.625s CKE = HIGH; CS# = HIGH DEEP POWER-DOWN Symbol IDD1 IDD2 IDD3 -8 50 150 35 -10 50 150 30 Units mA A mA Notes 3, 18, 19, 32 32 3, 12, 19, 32 3, 18, 19, 32 3, 12, 18, 19, 32, 33 34
IDD4 IDD5 IDD6 IZZ
50 100 2 10
50 80 2 10
mA mA mA A
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128Mb: x16 Mobile SDRAM Absolute Maximum Ratings Table 15: IDD7 - Self Refresh Current Options
Notes: 4; notes appear on page 43; VDD = VDDQ = +1.8V 0.1V Temperature Compensated Self Refresh Parameter/Condition Self Refresh Current: CKE < 0.2V - 4 Banks Open Maximum Temperature 85C 70C 45C 15C 85C 70C 45C 15C 85C 70C 45C 15C 85C 70C 45C 15C 85C 70C 45C 15C -8 / -10 200 160 140 120 160 130 120 110 130 120 110 100 120 110 100 90 115 105 95 90 Units A A A A A A A A A A A A A A A A A A A A Notes 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
Self Refresh Current: CKE < 0.2V - 2 Banks Open
Self Refresh Current: CKE < 0.2V - 1 Bank Open
Self Refresh Current: CKE < 0.2V - 1/2 Bank Open
Self Refresh Current: CKE < 0.2V - 1/4 Bank Open
Table 16: Capacitance
Note: 2; notes appear following on page 43 Paramter Input Capacitance: CLK Input Capacitance: All other input-only balls Input/Output Capacitance: DQ Symbol CI1 CI2 CIO MIN 1.5 1.5 3.0 MAX 4.0 4.0 6.0 Units pF pF pF Notes 29 30 31
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128Mb: x16 Mobile SDRAM Notes
Notes
1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +1.8V; TA = 25C; ball under test biased at 1.4V. f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-25C TA +85C for standard parts; 40C TA +85C for IT parts) is ensured. 6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q 30pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than tT (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every 2 clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 8ns for -8 and tCK = 9.6ns for -10. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns.
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128Mb: x16 Mobile SDRAM Notes
23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins at 7ns for -8 after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify 3 clocks. 27. tAC for -8 at CL = 3 with no load = 6ns, and is guaranteed by design. 28. Parameter guaranteed by design. 29. PC100 specifies a maximum of 4pF. 30. PC100 specifies a maximum of 5pF. 31. PC100 specifies a maximum of 6.5pF. 32. For -8, CL = 2, tCK = 9.6ns. For -10, CL = 3 and tCK = 9.6ns. 33. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 34. Deep power-down current is a nominal value at 25C. The parameter is not tested.
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128Mb: x16 Mobile SDRAM Initialize and Load Mode Register
Initialize and Load Mode Register
Figure 31: Initialize and Load Mode Register
Example Part Number: MT48H8M16LFF4-8 IT - MT48 VDD/ VDDQ Configuration Package Speed Temp
Operating Temp VDD/VDDQ 1.8/1.8V H None IT Extended Industrial
Configuration 8 Meg x16 8M16LF
Package 54-ball VFBGA (8mm x 8mm) 54-ball VFBGA (8mm x 8mm) Lead-Free F4 B4 -8 -10
Speed Grade 8ns 9.6ns
Notes: 1. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address 2. Optional refresh command. 3. Device timing is -10 with 104 MHz clock.
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128Mb: x16 Mobile SDRAM Timing Diagrams
Timing Diagrams
Figure 32: Power-Down Mode
T0 CLK tCK T1 tCL tCKS CKE tCKS tCKH tCH T2
(( )) (( ))
Tn + 1
Tn + 2
tCKS
(( ))
tCMS tCMH COMMAND
PRECHARGE NOP NOP
(( )) (( )) (( )) (( )) (( )) (( ))
NOP
ACTIVE
DQML, DQMU
A0-A9, A11
ALL BANKS
ROW
A10
SINGLE BANK
(( )) (( ))
ROW
tAS BA0, BA1
tAH
(( )) (( ))
(( ))
BANK(S)
High-Z
BANK
DQ Two clock cycles Precharge all active banks All banks idle, enter power-down mode
Input buffers gated off while in power-down mode All banks idle Exit power-down mode DON'T CARE
Notes: 1. Violating refresh requirements during power-down may result in a loss of data.
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 33: Clock Suspend Mode
T0
CLK
T1 tCK tCL
T2 tCH tCKS tCKH
T3
T4
T5
T6
T7
T8
T9
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ NOP NOP NOP NOP NOP WRITE NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN e 2
COLUMN m 2
tAS
A10
tAH
tAS
BA0, BA1
tAH
BANK BANK
tAC tAC
DQ
tOH
DOUT m
tHZ
DOUT m + 1
tDS
tDH
DOUT e + 1
tLZ
DOUT e
DON'T CARE UNDEFINED
Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled. 2. A9 and A11 are "Don't Care."
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 34: Auto Refresh Mode
T0
CLK tCK
T1
T2
tCH
(( )) (( )) (( ))
Tn + 1
tCL
(( )) (( )) (( ))
To + 1
CKE tCKS tCMS COMMAND tCKH tCMH
NOP AUTO REFRESH NOP
PRECHARGE
(( )) ( ( NOP )) (( )) (( ))
(( )) (( ))
AUTO REFRESH
NOP
(( )) ( ( NOP )) (( )) (( ))
(( )) (( )) (( )) (( ))
ACTIVE
DQMU, DQML
A0-A9, A11
ALL BANKS
ROW
A10
SINGLE BANK tAS BA0, BA1 tAH
(( )) (( ))
ROW
BANK(S)
(( )) (( )) (( )) tRP tRFC1 tRFC1
(( )) (( )) (( ))
BANK
DQ
High-Z
Precharge all active banks
DON'T CARE
Notes: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not required.
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 35: Self Refresh Mode
T0
CLK tCK
T1
tCH
tCL
T2
tCKS
> tRAS
(( )) (( ))
Tn + 1
(( )) (( )) (( )) (( ))
To + 1
To + 2
CKE tCKS tCMS COMMAND tCKH tCMH
NOP AUTO REFRESH
(( ))
PRECHARGE
(( )) (( )) (( )) (( )) (( )) (( ))
NOP ( (
(( ))
AUTO REFRESH
))
DQMU, DQML
(( )) (( )) (( )) (( )) (( )) (( ))
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
(( )) (( ))
t AS BA0, BA1
tAH
(( )) (( )) (( )) (( ))
BANK(S)
DQ
High-Z tRP Precharge all active banks
(( ))
(( ))
tXSR Enter self refresh mode Exit self refresh mode (Restart refresh time base)
CLK stable prior to exiting self refresh mode
DON'T CARE
Notes: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not required.
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 36: READ - Without Auto Precharge
T0
CLK
T1 tCK tCL
T2 tCH
T3
T4
T5
T6
T7
T8
tCKS
CKE
tCKH
tCMS tCMH
COMMAND ACTIVE NOP READ NOP NOP NOP
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
ROW
COLUMN m2
ROW ALL BANKS ROW
tAS
A10
tAH
ROW
tAS
BA0, BA1
tAH
BANK
DISABLE AUTO PRECHARGE BANK
SINGLE BANKS BANK(S) BANK
tAC tAC
DQ
tAC tOH
DOUT m+1
tAC tOH
DOUT m+2
tOH DOUT m
tOH
DOUT m+3
tLZ tRCD tRAS tRC CAS Latency
tHZ tRP
DON'T CARE UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. A9 and A11 are "Don't Care."
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 37: READ - With Auto Precharge
T0 CLK tCKS CKE tCMS tCMH COMMAND
ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
T8
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tAC DQ tRCD tRAS tRC tLZ CAS Latency
tAC tOH
DOUT m
tAC tOH
DOUT m + 1
tAC tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ tRP
DON'T CARE
UNDEFINED
Notes: 1. For this example, BL = 4 and CL = 2. 2. A9 and A11 are "Don't Care."
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 38: Single READ - Without Auto Precharge
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
tCK tCKS tCKH
tCL tCH
CKE
tCMS tCMH
COMMAND ACTIVE NOP READ NOP 3 NOP 3 PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
ROW
COLUMN m2
ROW ALL BANKS ROW
tAS
A10
tAH
ROW
tAS
BA0, BA1
tAH
BANK
DISABLE AUTO PRECHARGE BANK
SINGLE BANKS BANK(S) BANK
tAC
DQ
tOH
DOUT m
tLZ tRCD tRAS tRC CAS Latency
tHZ tRP
DON'T CARE UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. A9 and A11 are "Don't Care." 3. PRECHARGE command not allowed or tRAS would be violated.
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 39: Single READ - With Auto Precharge
T0 CLK tCKS CKE tCMS tCMH COMMAND
ACTIVE NOP NOP3 NOP3 READ NOP NOP ACTIVE NOP
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
T8
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tAC DQ tRCD tRAS tRC CAS Latency tRP
t OH
DOUT m
tHZ
DON'T CARE UNDEFINED
Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. A9 and A11 are "Don't Care." 3. PRECHARGE command not allowed or tRAS would be violated.
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 40: Alternating Bank Read Accesses
T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK tCKS CKE tCMS COMMAND tCMH tCKH
tCK
tCL tCH
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2
ROW
COLUMN b 2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK 0 BANK 3 BANK 3 BANK 0
BANK 0
tAC DQ tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD tLZ CAS Latency - BANK 0
tAC tOH
DOUT m
tAC tOH
DOUT m + 1
tAC tOH
DOUT m + 2
tAC tOH
DOUT m + 3
tAC tOH
DOUT b
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
DON'T CARE UNDEFINED
Notes: 1. For this example, BL = 4 and CL = 2. 2. A9 and A11 are "Don't Care."
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128Mb: x16 Mobile SDRAM Timing Diagrams Figure 41: READ - Full-Page Burst
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP NOP NOP NOP
T1 tCL tCH tCKH tCK
T2
T3
T4
T5
T6
(( )) (( ))
Tn + 1
Tn + 2
Tn + 3
Tn + 4
(( )) (( )) (( )) (( )) (( )) (( ))
ACTIVE
NOP
BURST TERM
NOP
NOP
tCMS DQMU, DQML
tCMH
tAS A0-A9, A11
tAH
COLUMN m 2
ROW
(( )) (( ))
tAS A10
tAH
ROW
(( )) (( ))
tAS BA0, BA1
tAH
BANK
BANK
(( )) (( ))
tAC tAC DQ tLZ tRCD CAS Latency tOH
DOUT m
tAC tOH
DOUT m+1
tAC ( ( tOH ) )
(( )) DOUT m+2 (( ))
tAC tOH
DOUT m-1
tAC tOH
DOUT m
tOH
DOUT m+1
256 (x16) locations within same row
tHZ
Full page completed Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command.
DON'T CARE UNDEFINED
Notes: 1. For this example, CL = 2. 2. A9 and A11 are "Don't Care." 3. Page left open; no tRP.
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM Timing Diagrams Figure 42: READ - DQM Operation
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP NOP NOP NOP NOP NOP
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2 ENABLE AUTO PRECHARGE
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK
DISABLE AUTO PRECHARGE BANK
tAC DQ tLZ tRCD CAS Latency
tOH
DOUT m
tAC
tAC tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ
tLZ
tHZ
DON'T CARE UNDEFINED
Notes: 1. For this example, CL = 2. 2. A9 and A11 are "Don't Care."
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM Timing Diagrams Figure 43: WRITE - Without Auto Precharge
T0
CLK
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
T7
T8
T9
tCKS
CKE
tCMS
COMMAND
tCMH
NOP WRITE NOP NOP NOP NOP PRECHARGE NOP ACTIVE
ACTIVE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 3 ALL BANKS ROW DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK ROW
ROW
tAS
A10
tAH
ROW
tAS
BA0, BA1
tAH
BANK
tDS
DQ
tDH DIN m
tDS
tDH
tDS
tDH
tDS
tDH
DIN m + 1
DIN m + 2
DIN m + 3 t WR 2 tRP
tRCD tRAS tRC
DON'T CARE
Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between and the PRECHARGE command, regardless of frequency. 3. A9 and A11 are "Don't Care."
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM Timing Diagrams Figure 44: WRITE - With Auto Precharge
T0
CLK
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
T7
T8
T9
tCKS
CKE
tCMS
COMMAND
tCMH
NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE
ACTIVE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 2 ENABLE AUTO PRECHARGE ROW ROW
ROW
tAS
A10
tAH
ROW
tAS
BA0, BA1
tAH
BANK BANK
BANK
tDS
DQ
tDH DIN m
tDS
tDH
tDS
tDH
tDS
tDH
DIN m + 1
DIN m + 2
DIN m + 3 tWR tRP
tRCD tRAS tRC
DON'T CARE
Notes: 1. For this example, BL = 4. 2. A9 and A11 are "Don't Care."
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM Timing Diagrams Figure 45: Single WRITE - Without Auto Precharge
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP 4 NOP 4 PRECHARGE NOP ACTIVE NOP
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAH
COLUMN m 3 ALL BANKS ROW DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK
tDS DQ tRCD tRAS tRC
tDH DIN m t WR 2 tRP
DON'T CARE
Notes: 1. 2. 3. 4.
For this example, BL = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 15ns is required between and the PRECHARGE command, regardless of frequency. A9 and A11 are "Don't Care." PRECHARGE command not allowed or tRAS would be violated.
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM Timing Diagrams Figure 46: Single WRITE - With Auto Precharge
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP3 NOP3 NOP3 WRITE NOP NOP NOP ACTIVE NOP
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2 ENABLE AUTO PRECHARGE
ROW
tAS A10
tAH
ROW
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tDS DQ tRCD tRAS tRC
tDH DIN m tWR tRP
DON'T CARE
Notes: 1. 2. 3. 4.
For this example, BL = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 15ns is required between and the PRECHARGE command, regardless of frequency. A9 and A11 are "Don't Care." WRITE command not allowed or tRAS would be violated.
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM Timing Diagrams Figure 47: Alternating Bank Write Accesses
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS DQMU, DQML tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2
ROW
COLUMN b 2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK 0 BANK 1 BANK 1 BANK 0
BANK 0
tDS DQ tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD
tDH DIN m
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH DIN b
tDS
tDH
tDS
tDH
tDS
tDH
DIN m + 1
DIN m + 2
DIN m + 3
DIN b + 1 tRP - BANK 0
DIN b + 2
DIN b + 3 tRCD - BANK 0
tWR - BANK 0
tRCD - BANK 1
tWR - BANK 1
DON'T CARE
Notes: 1. For this example, BL = 4. 2. A9 and A11 are "Don't Care."
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
61
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM Timing Diagrams Figure 48: Write - Full-Page Burst
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP
T1 tCL tCH tCKH tCK
T2
T3
T4
T5
(( )) (( ))
Tn + 1
Tn + 2
Tn + 3
(( )) (( )) (( )) (( ))
ACTIVE
NOP
BURST TERM
NOP
tCMS tCMH DQMU, DQML
(( )) (( ))
tAS A0-A9, A11
tAH
COLUMN m 1
ROW
(( )) (( ))
tAS A10
tAH
ROW
(( )) (( ))
tAS BA0, BA1
tAH
BANK
BANK
(( )) (( ))
tDS DQ tRCD
tDH
tDS
tDH
tDS
tDH
tDS
tDH
DIN m
DIN m + 1
DIN m + 2
DIN m + 3
(( )) (( ))
tDS
tDH
DIN m - 1 Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.2, 3 DON'T CARE
512 (x16) locations within same row
Full page completed
Notes: 1. 2. 3.
t
A9 and A11 are "Don't Care." WR must be satisfied prior to PRECHARGE command. Page left open; no tRP.
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
62
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM Timing Diagrams Figure 49: Write - DQM Operation
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP NOP NOP
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
ACTIVE
tCMS tCMH DQMU, DQML tAS A0-A9, A11 tAH
COLUMN m 2 ENABLE AUTO PRECHARGE
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
DISABLE AUTO PRECHARGE BANK
BANK
tDS DQ tRCD
tDH
DIN m
tDS
tDH
tDS
tDH
DIN m + 2
DIN m + 3
DON'T CARE
Notes: 1. For this example, BL = 4. 2. A9 and A11 are "Don't Care."
PDF: 09005aef80c97087/Source: 09005aef80c97015 MT48H8M16_2.fm - Rev. E 3/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
128Mb: x16 - Mobile SDRAM Package Dimensions
Package Dimensions
Figure 50: 54-Ball FBGA (8mm x 8mm)
0.65 0.05
SEATING PLANE C 0.10 C 54X O0.45 0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS 0.42. BALL A9 SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3% Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: O0.40 6.40 0.80 TYP BALL A1 ID SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID
BALL A1 4.00 0.05 C L 8.00 0.10
6.40
3.20 0.05
0.80 TYP
C L 3.20 0.05 4.00 0.05 1.00 MAX
8.00 0.10
Notes: 1. All dimensions are in millimeters.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.

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